ACARA Jobs
Digital Engineer
Apply- ID: 543146
- Posted: 9/3/2024
- Location: Linthicum, MD
- Category: Pro - Engineering
- Job Type: Temporary
- Duration: 9 - 12 Months
Are you a Digital Engineer looking to join one of the top Aerospace and Defense industries?
Are you looking to further your career and grow?
Do you have experience in the complete product life cycle of ASIC Design?
If you answered yes to those three questions, then apply today!
Acara Solutions seeks highly qualified candidates to work on-site with our client in Linthicum, MD. Interested?
Here's what you'd do:
- The client is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse Digital Technology Professionals.
- Qualified applicant will become part of the Digital Technologies department, which specializes in product designs for various applications from undersea to outer space.
- The individual will be responsible for the DFT (Design for Testability) aspects of ASIC Design.
Here's what you'll get:
Pay: $71.25/hr.
Hours: 40 hours/week.
Length: Temp (12 Months).
Sounds like a good fit?
APPLY TODAY
About Acara Solutions
Acara is a premier recruiting and workforce solutions provider-we help companies compete for talent. With a legacy of experience in various industries worldwide, we partner with clients, listen to their needs, and customize visionary talent solutions that drive desired business outcomes. We leverage decades of experience to deliver contingent staffing, direct placement, executive search, and workforce services worldwide.
- Bachelor's Degree in Electrical Engineering.
- Minimum of 9 years experience in the complete product life cycle of ASIC Design.
- Minimum of 9 years experience with Cadence, Mentor, or Synopsys test insertion and ATPG tools.
- Minimum of 9 years experience with hierarchical scan testing, IEEE-1500 or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG.
- Minimum of 9 years experience with memory BIST and logic BIST.
- Minimum of 9 years experience generating test patterns and analyzing and debugging test failures.
- Minimum of 9 years experience working with test engineers to implement ATPG vectors on tester hardware.
- Minimum of 9 years experience in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python, or Perl.
- Minimum of 9 years experience with ASIC development process.
- Minimum of 9 years experience in RTL coding and DFT methodologies.
- Effective communication and presentation skills and high proficiency in technical problem-solving
- Knowledge of Synthesis, P&R, and Static Timing Analysis.
- Successful candidates will thoroughly understand digital design concepts.
- This candidate will be able to operate in a team environment and collaborate across the different teams as necessary to accomplish the goals.
Additional Information:
- Upon offer of employment, the individual will be subject to a background check and a drug screen.
- In compliance with federal law, all persons hired will be needed to verify identity and eligibility to work in the United States and to complete the necessary employment eligibility verification form upon hire.
- Under the International Traffic in Arms Regulations (ITAR), all employees assigned to this client must provide documentation verifying their status as a 'U.S. Person,' as defined in ITAR clause 120.15. A U.S. Person is a protected individual under the anti-discrimination provisions of U.S. immigration laws.